1. Field of the Invention
The present invention relates to a method for reducing spurious erasing during programming of a memory array of a nonvolatile NROM.
2. Description of the Related Art
As is known, nonvolatile NROMs (nitride read-only memories) are formed by memory cells having an information-storage area of insulating material, namely silicon nitride. The general structure of a NROM cell is shown in FIG. 1. A NROM cell 1 is formed in a substrate 2 housing a first conductive region 3 and a second conductive region 4, separated by a channel region 5. On top of the channel region 5 is a triple insulating layer 10 formed by a first oxide region 11, a nitride region 12 and a second oxide region 13. A control gate region 14 extends on top of the insulating triple layer 10. A cell of this type is, for example, described in WO-A-99 07000, which is incorporated herein, by reference.
In cells of this type, the nitride region 12 operates as a charge local retention region. In fact, during programming, if a high programming voltage is applied to the first conductive region 3, electrons flow towards the end of the nitride layer near the first conductive region 3 (which, in this situation, acts as the drain region in nonvolatile cells of the EPROM or flash type), and these electrons remain trapped in this area (first storage area 18 in FIG. 1). If, instead, a high programming voltage is applied to the second conductive region 4, electrons flow towards the end of the nitride layer near the second conductive region 4 (which, in this situation, acts as the drain region), and these electrons remain trapped in this area (second storage area 19).
Since programming of each storage area 18, 19 determines a different electrical behavior of the cell 1, according to whether the first storage area 18, the second storage area 19, neither of them or both of them are programmed, four different electrical configurations are obtained, and the cell is able to store two bits.
Reading of the cell entails verification of the programmed or non-programmed state of both of the storage areas 18, 19. To this aim, when the state of the first storage area 18 is to be read, a read voltage (for example, 1.5 V) is applied to the second conductive region 4 (drain region), the control gate region 14 is biased (for example, at 3 V), and the second conductive region 3 (source) is grounded. A depletion region is therefore created in the channel region 5 and near the second conducting region 4. Furthermore, an inversion region is created along the channel 5. If the first storage area 18 has not been programmed, the depletion region reaches the first conductive region 3, the cell 1 is conductive, and a xe2x80x9c0xe2x80x9d is read. If, instead, the first storage area 18 has been programmed, the depletion region is unable to reach the first conductive region 3, the cell 1 is off, and a xe2x80x9c1xe2x80x9d is read.
Likewise, by inverting the biasing voltages and then applying a read voltage to the first conductive region 3 and connecting the second conductive region 4 to ground, it is possible to detect whether the second storage area 19 has been programmed (bit xe2x80x9c1xe2x80x9d) or not (bit xe2x80x9c0xe2x80x9d).
Erasing of this type of cell is performed via injection of holes in the storage areas 18, 19, which holes combine with the electrons and neutralize the effect of the stored charge.
Since erasing does not entail extraction of charges from the storage area or areas, as, instead, for standard nonvolatile memories, but entails injection of charges of opposite sign, the writing capacity of a cell of this type is limited by the maximum storage capacity of the nitride layer 12, and, once the latter is reached, the cell is saturated and is no longer usable (low cycling).
For this reason, it becomes essential to reduce the amount of charges injected each time in the storage areas 18, 19. Furthermore, it is also important to prevent undesired injection of charges due to spurious effects.
In order to control the quantity of charge injected during programming, the programming voltage is kept as low as possible, and programming is interrupted once the threshold voltage is reached. To this end, the programming voltage is supplied as pulses of increasing amplitude, and after each pulse the threshold reached is verified.
In order to eliminate spurious injection, it is instead important to prevent situations that are dangerous in this regard. One of these situations occurs, for instance, during programming of a cell, owing to the unavoidable biasing of the deselected cells, which are electrically connected to the cell to be programmed.
In fact, like other types of memory, nonvolatile NROMs are characterized by an organization of the memory array wherein a number of cells have conductive regions connected to one another by bitlines. In particular, the cells form an array aligned along rows and columns, wherein, for example, the cells arranged in a same row are connected to a same wordline WL forming the gate regions 14 of the cells themselves, and the cells arranged in a same column are connected to the same bitlines BL1, BL2 forming the first and the second conductive regions 3, 4 (see FIG. 2). Furthermore, frequently two adjacent cells in the direction of the rows share a same conductive region 3, 4. For instance, as illustrated in FIG. 3, a cell 1 shares the first conductive region 3 (formed, for example, by the first bitline BL1n) with a cell 1a set on its left, and the second conductive region 4 (formed by the bitline BL2n) with a cell 1b set on its right (virtual ground architecture).
Consequently, any voltage applied to a bitline 3, 4 is common to all the cells connected to the same line. Consequently, during programming of the memory array, when a cell of a generic packet is programmed, also the cells connected to the same bitlines 3, 4 are biased. In this situation, the deselected cells connected to the bitline biased at programming voltage and thus arranged in the same column and in the adjacent column to the cell to be programmed, are in a erase-like or spurious erasing configuration. In fact, in order to prevent programming, a gate voltage VG=0 V is applied to these cells. However, the configuration with a first conductive region at a high voltage and the gate region at 0 V is precisely the erasing configuration of this type of memory.
As a result, on the cells connected to the cell to be programmed spurious injection conditions are present, which determine a degrading of the programming levels previously stored in these cells.
The spurious erasing that occurs at each programming cycle is quite mild thanks to the limited programming voltage during programming (values ranging from 4 V to 6.5 V in case of programming and values ranging from 7.5 V to 8.2 V in case of an effective erasing). Nevertheless, spurious erasing, even if mild, has some negative repercussions both on the reliability of the cell modification system and on the number of cells that can be connected to the same source and drain lines.
In fact, even though the variation in the threshold voltage does not manifest itself at a visible level (thanks to the limited time duration of the programming pulse), spurious erasing causes undesired accumulation of holes inside the cell. Furthermore, the accumulation occurs with charges that have paths that favor their trapping in the intermediate part of the nitride region, above the channel region of the cell. This entails a limitation of the cycling characteristics of the device, which has negative effects that are particularly marked in the case of memories of the type considered, for the reasons explained above.
The above mentioned problem of spurious erasing is the more severe the higher the programming voltage and can be particularly limiting in case of lots of cells having a low programming speed. Furthermore, the problem is all the more felt the longer the bitlines, since in this case programming of a single cell causes spurious erasing of a high number of cells. In addition, as the likelihood of programming more cells connected to the same bitlines increases, on the one hand, the likelihood that the sum of the spurious erasing effects causes an erasing proper also increases, and, on the other hand, the likelihood that a cell that has just been programmed (the injected charge whereof is as limited as possible to increase cycling, as explained above) being able to exit from the programmed condition just reached increases. In order to reduce the incidence of spurious erasing, it is therefore necessary to provide a high number of sectors or subsectors, with bitlines of reduced length. The increase in the number of bitlines (with breaking-up into a lot of lines) makes it necessary to provide a high number of selectors, one for each bitline. However, since the selectors and the corresponding control lines involve a large occupation of area, the result is a large overall occupation of the memory array.
The aim of the present invention is therefore to reduce the problem of spurious erasing during programming of NROM cells, so as to increase cycling and reduce the dimensions of the memory array.
According to the invention, a method for programming an NROM nonvolatile memory array and a corresponding memory device are provided.
An embodiment of the invention provides a method for programming a memory array of a NROM nonvolatile memory comprising a plurality of memory cells organized in rows and columns and provided with first conductive regions formed in a semiconductor body and connected to first bitlines, second conductive regions formed in the semiconductor body and connected to second bitlines, charge storage regions of insulating material, formed on top of the semiconductor body, and gate regions arranged on top of the charge storage regions and connected to respective wordlines. The method comprises the steps of applying a first voltage to a selected one of the wordlines, the first voltage having a first value with respect to the semiconductor body, and applying a second voltage having a second non-zero value, lower than the first value, to a plurality of the wordlines excluding the selected wordline.
Another embodiment of the invention provides a an NROM device having a memory array, including a first plurality of bitlines, a second plurality of bitlines, a plurality of wordlines, a plurality of memory cells, and a programming circuit. The memory cells are organized in rows and columns and provided with first conductive regions formed in a semiconductor body, each connected to one of the first plurality of bitlines, second conductive regions formed in the semiconductor body, each of the second conductive regions connected to one of the second plurality of bitlines, charge storage regions of insulating material formed on top of the semiconductor body, and gate regions arranged on top of the charge storage regions and connected to respective ones of the plurality of wordlines. A programming circuit for a selected cell is connected to a selected one of the plurality of wordlines. The programming circuit comprises a plurality of drivers, including a first driver and second drivers, the first driver supplying a first voltage of a first value with respect to the semiconductor body to the selected one of the wordlines, and the second drivers configured to supply a second voltage having a second non-zero value, lower than the first value, to each of the plurality of the wordlines, excluding the selected wordline.